1. Field of the Invention
The present invention relates to the formation of structures in microelectronic devices such as integrated circuit devices. More particularly, the invention relates to the formation of vias, interconnect metallization and wiring lines using multiple low dielectric constant intermetal dielectrics.
2. Description of the Related Art
In the production of microelectronic devices, integrated circuits utilize multilevel wiring structures for interconnecting regions within devices and for interconnecting one or more devices within the integrated circuits. In forming such structures, it is conventional to form a first lower level wiring lines, then an interlevel dielectric layer and then to form second level wiring lines. One or more metal filled vias are typically formed in the interlevel dielectric to connect the first and second level wiring lines.
One conventional method for forming a two level wiring structure is to first form a two level interconnect structure over a substrate. The surface of a substrate may be the surface of a silicon device structure or the surface of substrate may be an insulating layer. An oxide layer is typically deposited over the substrate by chemical vapor deposition. The first level interconnect structures are defined by a conventional photolithography process which forms openings through the oxide layer where the first level interconnects will be formed. Generally, the openings expose portions of conductors in the substrate to which interconnects are formed. The openings are filled with a metal interconnect to form the interconnect and form a metal plug. Then a layer of metal such as aluminum is deposited over the surface of the oxide layer and over the metal plug to a thickness appropriate for second level wiring lines. The metal layer is then patterned into the second level wiring lines. The second level wiring lines are defined in a conventional photolithography process by providing a layer of photoresist over the metal layer, exposing the photoresist through a mask and removing portions of the exposed photoresist layer to form a photoresist etch mask. The portions of the metal layer exposed by openings in the photoresist mask are then removed by etching and the photoresist mask is removed by ashing. After the two level interconnect structure is formed, it is necessary to provide an intermetal dielectric (IMD) layer between the second level wiring lines and covering the second level wiring lines to accommodate further processing of the integrated circuit device. In the past, the intermetal dielectric layer might consist of one or more layers of oxide deposited by plasma enhanced chemical vapor deposition or other processes.
Prior art integrated circuits produced by single or dual damascene processes with Cu interconnects and low dielectric-constant (k) intermetal dielectrics have used only one kind of low-k dielectric, either inorganic, organic or a hybrid of these two kinds. This conventional approach of using the same kind of low-k dielectric for both metal-level and via-level IMD""s has limited process integration and implementation options. As a result, additional processing steps and added cost are required. It is desirable whenever possible to reduce the number of processing steps required to form a device because reducing the number of processing steps shortens the time required to produce the device and because eliminating processing steps improves yields and so reduces costs.
The present invention uses two or more dissimilar low-k dielectrics for the intermetal dielectrics of Cu-based dual damascene backends of integrated circuits. The use of both organic and inorganic low-k dielectrics offers several advantages due to the significantly different plasma etch characteristics of these two kinds of dielectrics. One dielectric serves as an etchstop in etching the other dielectric. No additional oxide or nitride etchstop layer is required. High performance is achieved due to the lower parasitic capacitance resulting from the use of low-k dielectrics.
The invention provides an integrated circuit structure which comprises a substrate and (a) an inorganic layer on the substrate which comprises a pattern of metal lines on the substrate and an inorganic dielectric on the substrate between the metal lines; and (b) an organic layer on the inorganic layer which comprises an organic dielectric having metal filled vias therethrough which connect to the metal lines of the inorganic layer. Preferably the integrated circuit structure comprises (c) an additional inorganic layer on the organic layer which comprises a pattern of additional metal lines on the organic layer and an inorganic dielectric on the organic layer between the additional metal lines; and (d) an additional organic layer on the additional inorganic layer which comprises an organic dielectric having metal filled vias therethrough which connect to the additional metal lines of the additional inorganic layer.
The invention also provides an integrated circuit structure which comprises a substrate and (a) an organic layer on the substrate which comprises a pattern of metal lines on the substrate and an organic dielectric on the substrate between the metal lines; and (b) an inorganic layer on the organic layer which comprises an inorganic dielectric having metal filled vias therethrough which connect to the metal lines of the organic layer. Preferably the integrated circuit structure comprises (c) an additional organic layer on the inorganic layer which comprises a pattern of additional metal lines on the inorganic layer and an organic dielectric on the inorganic layer between the additional metal lines; and (d) an additional inorganic layer on the additional organic layer which comprises an inorganic dielectric having metal filled vias therethrough which connect to the additional metal lines of the additional organic layer.
The invention also provides a dielectric coated substrate which comprises:
(a) a first dielectric composition film on a substrate; and
(b) a second dielectric composition film on the first dielectric composition film;
wherein the first dielectric composition and the second dielectric composition have substantially different etch resistance.
The invention further provides a process for producing an integrated circuit structure which comprises
(a) providing a substrate which comprises a pattern of metal lines on the substrate and a dielectric on the substrate between the metal lines;
(b) depositing an organic dielectric layer on the substrate;
(c) depositing an inorganic dielectric layer on the organic dielectric;
(d) etching a pattern of vias through the inorganic dielectric layer;
(e) etching a pattern of vias through the organic dielectric layer which correspond to the pattern of vias through the inorganic dielectric layer;
(f) applying a photoresist to the top of the inorganic dielectric layer and filling the vias in the organic dielectric layer and the inorganic dielectric layer with photoresist;
(g) imagewise removing a portion of the photoresist from the top of the inorganic dielectric layer; and removing a portion and leaving a portion of the photoresist through a thickness of the inorganic dielectric layer;
(h) removing part of the inorganic dielectric layer underlying the portions of the photoresist removed from the top of the inorganic dielectric layer to form trenches in the inorganic dielectric layer;
(i) removing the balance of the photoresist from the top of the inorganic dielectric layer and from the vias;
(j) filling the vias in the organic dielectric and the trenches in the inorganic dielectric with a metal.
The invention still further provides a process for producing an integrated circuit structure which comprises
(a) providing a substrate, which comprises a pattern of metal lines on the substrate and a dielectric on the substrate between the metal lines;
(b) depositing an organic via level dielectric on the substrate;
(c) depositing an thin inorganic dielectric layer on the organic via level dielectric;
(d) imagewise patterning and removing a portion of the thin inorganic dielectric layer thus defining vias through the thin inorganic dielectric layer;
(e) depositing a thin organic dielectric etchstop material layer on the thin inorganic dielectric layer and filling the vias in the thin inorganic dielectric layer with the organic dielectric material;
(f) depositing a metal level inorganic dielectric layer on the organic dielectric etchstop layer;
(g) imagewise patterning and removing a portion of the metal level inorganic dielectric layer down to the organic dielectric etchstop material layer to form trenches in the metal level inorganic dielectric layer;
(h) removing the portion of the organic dielectric etchstop material layer underlying the corresponding removed portion of the metal level inorganic dielectric to form trenches therein, and removing the organic etchstop material from the vias in the thin inorganic dielectric layer;
(i) removing the portion of the organic via level dielectric layer underlying the thin inorganic dielectric layer thus forming vias through the organic via level dielectric layer down to the metal lines;
(j) filling the vias in the via level organic dielectric layer and the thin inorganic dielectric layer, and trenches in the organic dielectric etchstop layer and metal level inorganic dielectric layer with a metal.
The invention also provides a process for producing an integrated circuit structure which comprises
(a) providing a substrate, which comprises a pattern of metal lines on the substrate and a dielectric on the substrate between the metal lines;
(b) depositing an organic via level dielectric layer on the substrate;
(c) depositing an thin inorganic dielectric layer on the organic via level dielectric;
(d) depositing a thin organic dielectric etchstop material layer on the thin inorganic dielectric layer;
(e) depositing a metal level inorganic dielectric layer on the organic dielectric etchstop layer;
(f) imagewise patterning and removing a portion of the metal level inorganic dielectric layer down to the organic dielectric etchstop material layer to form vias in the metal level inorganic dielectric layer;
(g) removing the portion of the organic dielectric etchstop material layer underlying the corresponding removed portions of the metal level inorganic dielectric layer to form vias in the organic dielectric etchstop material layer;
(h) removing the portion of the thin inorganic dielectric layer underlying the corresponding removed portions of the organic dielectric etchstop material layer to form vias in the thin inorganic dielectric layer;
(i) covering the top of the metal level inorganic dielectric layer with a photoresist and filling the vias in the metal level inorganic dielectric layer, the organic dielectric etchstop material layer and the thin inorganic dielectric layer with photoresist;
(j) imagewise patterning and removing a portion of the photoresist from the top of the metal level inorganic dielectric layer; and removing a portion and leaving a portion of the photoresist through a thickness of the metal level inorganic dielectric layer;
(k) removing part of the metal level inorganic dielectric layer underlying the portions of the photoresist removed from the top of the inorganic dielectric layer to form trenches in the metal level inorganic dielectric layer;
(l) removing the balance of the photoresist from the top of the metal level inorganic dielectric layer and from the vias; and removing the portion of the organic dielectric etchstop material layer underlying the trenches until the thin inorganic dielectric layer is reached;
(m) removing the portion of the organic via level dielectric layer underlying the vias in the thin inorganic dielectric layer;
(n) filling the vias in the via level organic dielectric layer and the thin inorganic dielectric layer, and trenches in the organic dielectric etchstop layer and metal level inorganic dielectric layer with a metal.
The invention furthermore provides a process for producing an integrated circuit structure which comprises
(a) providing a substrate, which comprises a pattern of metal lines on the substrate and a dielectric on the substrate between the metal lines;
(b) depositing an organic via level dielectric layer on the substrate;
(c) depositing an thin inorganic dielectric layer on the organic via level dielectric
(d) depositing a thin organic dielectric etchstop material layer on the thin inorganic dielectric layer;
(e) depositing a metal level inorganic dielectric layer on the organic dielectric etchstop layer;
(f) imagewise patterning and removing a portion of the metal level inorganic dielectric layer down to the organic dielectric etchstop material layer to form vias in the metal level inorganic dielectric layer;
(g) removing the portion of the organic dielectric etchstop material layer underlying the corresponding removed portions of the metal level inorganic dielectric layer to form vias in the organic dielectric etchstop material layer;
(h) removing the portion of the thin inorganic dielectric layer underlying the corresponding removed portions of the organic dielectric etchstop material layer to form vias in the thin inorganic dielectric layer;
(i) removing the portion of the organic via level dielectric layer underlying the corresponding removed portions of the thin inorganic dielectric layer to form vias in the organic via level dielectric layer;
(j) covering the top of the metal level inorganic dielectric layer with a photoresist and filling the vias in the metal level inorganic dielectric layer, the organic dielectric etchstop material layer, the thin inorganic dielectric layer and the organic via level dielectric layer with photoresist;
(k) imagewise patterning and removing a portion of the photoresist from the top of the inorganic dielectric layer; and removing a portion and leaving a portion of the photoresist through a thickness of the metal level inorganic dielectric layer;
(l) removing part of the metal level inorganic dielectric layer underlying the portions of the photoresist removed from the top of the inorganic dielectric layer to form trenches in the metal level inorganic dielectric layer;
(m) removing the balance of the photoresist from the top of the metal level inorganic dielectric layer and from the vias; and removing the portion of the organic dielectric etchstop material layer underlying the trenches until the thin inorganic dielectric layer is reached;
(n) filling the vias in the via level organic dielectric layer and the thin inorganic dielectric layer, and trenches in the organic dielectric etchstop layer and metal level inorganic dielectric layer with a metal.